1. Field
Exemplary embodiments of the present invention relate to a delay circuit and a signal delay method.
2. Description of the Related Art
In the field of integrated circuit, various circuits included in integrated circuits do not operate alone, but operate while exchanging signals (for example, data) with other circuits. In general in order that a circuit A and a circuit B interact with each other, the circuit A requests the circuit B to do an operation, and a predetermined standby time is required until the circuit B operates in response to the request. The standby time is called latency. The reason that the standby time is required is for increase transmission efficiency of signal between the circuit A and the circuit B and ensuring the time for the internal operation of the circuit B.
A memory controller and a memory may be considered as an example of interaction between two or more circuits included in an integrated circuit system. When the memory controller applies a write command to the memory, the memory stores the data input from the memory controller in a memory cell. However, the memory cannot receive the data from the memory controller, upon receiving the write command. This is because the memory needs time to internally prepare for storing the data. The factor defined for the preparation is write latency.
In general, an address for designating the memory cell to store data in is also applied with the write command. However, the data to be stored is input to the memory after the write latency passes from when the write command is applied, so that it is necessary to delay the address for the write latency.
Meanwhile, over DDR2 and DDR3 SDRAM, a new concept, an AL (Additive Latency) has been introduced to increase efficiency of a data bus. Therefore, even if read/write commands or an address is applied from the outside before tRCD (RAS to CAS delay), it is delayed as much as the additive latency, internal read/write commands or an internal address is generated after the tRCD, and a read/write operation of a semiconductor memory device is performed. The additive latency is set by an EMRS, and the additive latency (AL) is fixed at a specific value in the DDR2 SDRAM, but the additive latency (AL) is 0, CL-1, and CL-2, interlocked with the CAS latency (CL). The additive latencies are applied to both read/write commands, and accordingly the address should be delayed as much as the additive latency.
Hereinafter, a delay circuit of a memory which delays a read command or a write command will be described.
FIG. 1 is a diagram illustrating the configuration of a conventional delay circuit.
As illustrated in FIG. 1, the conventional delay circuit includes a first delay unit 110 configured to generate a delayed read command RD_DEL by delaying a read command RD and a second delay unit 120 configured to generate a delayed write command WT_DEL by delaying a write command WT. The delay circuit generates a delayed read command RD_DEL or a delayed write command WT_DEL by delaying a read command RD or a write command WT. It is described when the delay circuit of FIG. 1 generates a delayed read command RD_DEL and a delayed write command WT_DEL by delaying a read command RD and a write command WT within the range of 1 to 7 clock cycles. The range of delay values where the delay circuit can delay the command RD and WT may depend on the design. The delay value of the delay circuit delaying the commands RD and WT may be an additive latency.
Hereinafter, the delay circuit will be described with reference to FIG. 1.
The first delay unit 110 includes a plurality of first shifting units D11 to D18 and a plurality of first selection units S11 to S13, which are connected in series, respectively. The shifting unit. D11 in the first shifting units D11 to D18 outputs an applied read command RD in synchronization with a clock CLK. The shifting units D12 to D18 outputs signals input to them by delaying the signals by one clock cycle in synchronization with the clock CLK. The first shifting units may be D-flip flops.
The first selection units S11 to S13 selects a first shifting unit through which the applied read command RD passes, in the first shifting units D11 to D18 in response to delay information DEL<0:3>. For example, the delay value of the first delay unit 110 is selected as one clock cycle, the selection units S11 to S13 do not pass the applied read command RD through all the shifting units D12 to D17 in response to delay information (DEL<0:3>). Therefore, the read command RD is delayed by one clock cycle by the shifting unit D18 and transmitted as a delayed read command RD_DEL (all the selection units S11, S12 and S13 select and output the signal input to the terminal 0). For example, the delay value of the first delay unit 110 is selected as five clock cycles, the selection units S11 to S13 pass the applied read command RD through all the shifting units D12 to D15 in response to delay information (DEL<0:3>). The output of the shifting unit D15 is transmitted as a delayed read command RD_DEL through the shifting unit D18 (the selection units S11 and S12 select and output the signal input to the terminal 1 and the selection unit S13 selects and outputs the signal input to the terminal 0). For example, the delay value of the first delay unit 110 is selected as six clock cycles, the selection units S11 to S13 pass the applied read command RD through all the shifting units D12 to D16 in response to delay information (DEL<0:3>). The output of the shifting unit D16 is transmitted as a delayed read command RD_DEL through the shifting unit D18 (all the selection units S11, S12, and S13 select and output the signal input to the terminal 1).
The second delay unit 120 includes a plurality of second shifting units D21 to D28 and a plurality of second selection units S21 to S23, which are connected in series, respectively. The second delay unit 120 has the same configuration and operation as those of the first delay unit 110, except that they generate a delayed write command WT_DEL by delaying a write command WT.
In the delay circuits of the related art, the first delay unit 110 and the second delay unit 120 both include the shifting units D11 to D18 and D21 to D28, respectively, for delaying applied commands RD and WT by one clock cycle. In general, the shifting unit includes a D-flip flop and the D-flip flop occupies a large area and consumes a large amount of current. Therefore, as the first delay unit 110 and the second delay unit 120 each include a plurality of D-flip flops, the area and the consumed current of the delay circuit are large.